1. Field of the Invention
The present invention relates to a flip-flop circuit employing an MTCMOS technology and, more particularly, to a flip-flop circuit employing an MTCMOS technology capable of retaining a former state of sleep mode when the state of the system is converted from sleep mode to active mode.
2. Description of the Related Art
An MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technology is advantageous for improving an operation speed of a logic circuit 10 as shown in FIG. 1, by supplying a power supply voltage (or ground voltage) to the logic circuit 10 having a relatively low Vth (threshold voltage) as a MOS (Metal Oxide Semiconductor) transistor MP1 or MN1 is turned on in active mode, i.e., in power on mode, and for decreasing a leakage current or sub-threshold current of the logic circuit by cutting off the power supply voltage (or the ground voltage) to the logic circuit as the MOS transistor is turned off in sleep mode. The MOS transistor MP1 or MN1 having a relatively high Vth is connected in series between the power supply voltage (or the ground voltage) and the logic circuit 10. The MTCMOS technology is especially useful to decrease power consumption of an LSI (Large Scale Integration) chip for mobile applications in which the time in sleep mode is substantially longer than that in active mode. However, the MTCMOS technology has a problem that data stored in a latch or a flip-flop of the logic circuit in power off mode, i.e., sleep mode are lost. In the flip-flop circuit employing the MTCMOS technology, various circuits, which have solved the data loss problem in sleep mode, have been disclosed. FIG. 2 illustrates a prior art D type flip-flop circuit capable of retaining data in sleep mode, which is disclosed in IEEE JOURNAL OF SOLID STATE CIRCUIT, Vol. 32, No. 6, Satoshi Shigematsu, 1997. The D type flip-flop circuit shown in FIG. 2 is provided with a data keeper 230 for storing data in sleep mode and outputting the stored data in sleep mode to a master latch unit 210 and a slave latch unit 220 when the state of the system is restored to active mode so that an output of the flip-flop circuit retains a former state. In the circuit in FIG. 2, the logic circuit units 210 and 220 employ a low Vth transistor to increase an operation speed and the data keeper 230 uses a high Vth transistor to decrease a leakage current. In addition, the data keeper 230 is directly connected to the power supply voltage and the ground since it should be operated in sleep mode.
However, the prior art D type flip-flop circuit as shown in FIG. 2 have difficulties that the data keeper 230 should be additively inserted in the circuit to retain the data, data retaining control signals B1, B1B, B2 and B2B should be used to control a data read/write operation due to a co-relationship of a former clock signal and data on the conversion from sleep mode to active mode, and a control circuit for controlling these data retaining control signals should be performed in a top level of the circuit design step.